The present invention relates to a dynamic type semiconductor memory device having refreshing function.
Dynamic random access memories (DRAM) developed these days have a self-refreshing function for the reasons that the construction of means arranged around the memory can be simplified and that battery back-up operation can be easily achieved at the time of power source accident. The self-refreshing function means that data stored in the memory is refreshed independently of external circuits of the memory when refreshing input signal REF is set low and row address strobe signal RAS is set high. This self-refreshing function is achieved by means of a timer circuit which is rendered operative, when refreshing input signal REF becomes low, to generate a pulse every lapse of a predetermined time period, and a counter circuit which counts pulses supplied from the timer circuit to generate a refreshing row address signal so as to refresh memory data in every row. When the DRAM is devised to have this self-refreshing function, the construction of battery back-up system can be simplified and memory data can also be held with reliability.
When the memory device of this type is to carry out the self-refreshing operation, clock pulses are continuously applied to a row address buffer and a row decoder through such a clock pulse generating circuit as disclosed by U.S. Pat. No. 3,969,706, for example, to perform an active cycle during which memory data in memory cells on a selected row are refreshed. Clock pulses are then applied to the row decoder and a sense amplifier/bit line precharge circuit to perform a precharge cycle during which the row decoder and the bit line are precharged. In case of carrying out the self-refreshing operation, the following currents are consumed in the memory device. That is, currents flowing through the clock pulse generating circuit and the row address buffer are superposed to make an operation current shown by a broken line A in FIG. 1, and a current resulting from the superposition of currents flowing through the clock pulse generating circuit and the row decoder and shown by a broken line B in FIG. 1 flows through a power source line (not shown) just after the current shown by the broken line A in FIG. 1 is flows. Finally, a total current shown by a solid line S1 in FIG. 1 flows through the power source line in the active cycle. On the other hand, currents flowing through the clock pulse generating circuit and the row decoder are superposed in the precharge cycle to make an operation current shown by a broken line C in FIG. 1, and a current resulting from the superposition of currents flowing through the clock pulse generating circuit and the sense amplifier/bit line precharge circuit and shown by a broken line D in FIG. 1 flows through the power source line just after the current shown by the broken line C in FIG. 1 flows. A total current shown by a solid line S2 flows through the power source line in the precharge cycle. When the self-refreshing operation is achieved by the DRAM having 64k bits, for example, peak value of the total currents S1 and S2 is about 60 mA.
In the case of the memory device provided with 128 units of the 64-Kbit DRAMs and having a memory capacity of 1M byte, for example, the 128-unit DRAMs are made operative substantially synchronizingly and a current having a peak value of 60 mA.times.128.apprxeq.7.7A therefore flows through the power source line when the self-refreshing operation is carried out by the back-up battery at the time of power source accident. Since a large current like this flows through the power source line, the back-up battery employed must be of large capacity. When the battery employed is of small capacity, the power source voltage greatly fluctuates at the time when a large current flows through the power source line, possibly preventing the memory device from carrying out normal operation and from holding memory data.